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DATA SHEET
4GB Registered DDR2 SDRAM DIMM
EBE41RE4ACFA (512M words x 72 bits, 2 Ranks)
Specifications
* Density: 4GB * Organization 512M words x 72 bits, 2 ranks * Mounting 36 pieces of 1G bits DDR2 SDRAM sealed in FBGA * Package: 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) * Power supply: VDD = 1.8V 0.1V * Data rate: 667Mbps/533Mbps/400Mbps (max.) * Eight internal banks for concurrent operation (components) * Interface: SSTL_18 * Burst lengths (BL): 4, 8 * /CAS Latency (CL): 3, 4, 5 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles: 8192 cycles/64ms Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data referenced to both edges of DQS * Posted /CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * /DQS can be disabled for single-ended Data Strobe operation * 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2K bits EEPROM) for Presence Detect (PD)
Document No. E1052E30 (Ver.3.0) Date Published December 2007 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007
EBE41RE4ACFA
Ordering Information
Data rate Mbps (max.) 667 533 400 Component 1 JEDEC speed bin* (CL-tRCD-tRP) DDR2-667 (5-5-5) DDR2-533 (4-4-4) DDR2-400 (3-3-3) Contact pad Gold
Part number EBE41RE4ACFA-6E-E EBE41RE4ACFA-5C-E EBE41RE4ACFA-4A-E
Package 240-pin DIMM (lead-free)
Mounted devices EDE1104ACSE-8E-E EDE1104ACSE-6E-E EDE1104ACSE-8E-E EDE1104ACSE-6E-E EDE1104ACSE-8E-E EDE1104ACSE-6E-E
Note: 1. Module /CAS latency = component CL + 1.
Pin Configurations
Front side 1 pin 64 pin 65 pin 120 pin
121 pin Back side
184 pin 185 pin
240 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS /RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS
Pin No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
Pin name A4 VDD A2 VDD VSS VSS VDD NC/Par_In VDD A10 BA0 VDD /WE /CAS VDD /CS1 ODT1 VDD VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34
Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
Pin name VSS DQ4 DQ5 VSS DQS9 /DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DQS10 /DQS10 VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DQS11
Pin No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
Pin name VDD A3 A1 VDD CK0 /CK0 VDD A0 VDD BA1 VDD /RAS /CS0 VDD ODT0 A13 VDD VSS DQ36 DQ37 VSS DQS13 /DQS13 VSS DQ38 DQ39
Data Sheet E1052E30 (Ver.3.0)
2
EBE41RE4ACFA
Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Pin name /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS /DQS3 DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS /DQS8 DQS8 VSS CB2 CB3 VSS VDD CKE0 VDD BA2 NC/ /Err_Out VDD A11 A7 VDD A5 Pin No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin name DQ35 VSS DQ40 DQ41 VSS /DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS SA2 NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS /DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL Pin No. 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin name /DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS12 /DQS12 VSS DQ30 DQ31 VSS CB4 CB5 VSS DQS17 /DQS17 VSS CB6 CB7 VSS VDD CKE1 VDD NC NC VDD A12 A9 VDD A8 A6 Pin No. 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pin name VSS DQ44 DQ45 VSS DQS14 /DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS NC NC VSS DQS15 /DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS16 /DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
Data Sheet E1052E30 (Ver.3.0)
3
EBE41RE4ACFA
Pin Description
Pin name A0 to A13 A10 (AP) BA0, BA1, BA2 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In*
2 2
Function Address input Row address Column address Auto precharge Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground ODT control Reset pin (forces register and PLL inputs low) * Parity bit for the address and control bus Parity error found on the address and control bus No connection
1
A0 to A13 A0 to A9, A11
/Err_Out* NC
Notes: 1. Reset pin is connected to both OE of PLL and reset to register. 2. NC/ /Err_Out (Pin No. 55) and NC/Par_In (Pin No. 68) are for optional function to check address and command parity.
Data Sheet E1052E30 (Ver.3.0)
4
EBE41RE4ACFA
Serial PD Matrix
Byte No. Function described 0 1 2 3 4 5 6 7 8 9 Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 Bit5 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 1 Bit3 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 1 Bit2 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 Bit1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Bit0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 Hex value 80H 08H 08H 0EH 0BH 61H 48H 00H 05H 30H 3DH 50H 45H 50H 60H 02H 82H 04H 04H 00H 0CH 08H 38H 01H 01H 00H 03H 3DH 50H 50H 60H 50H 60H 3CH 1EH Comments 128 bytes 256 bytes DDR2 SDRAM 14 11 2 72 0 SSTL 1.8V 3.0ns*
1
Voltage interface level of this assembly 0 DDR SDRAM cycle time, CL = 5 -6E -5C -4A 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
3.75ns* 5.0ns*
1
1
10
SDRAM access from clock (tAC) -6E -5C -4A
0.45ns* 0.5ns* 0.6ns* ECC 7.8s x4 x4 0 4,8 8 3, 4, 5
1 1
1
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width Reserved SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency DIMM Mechanical Characteristics DIMM type information SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CL = 4 -6E, -5C -4A Maximum data access time (tAC) from clock at CL = 4 -6E, -5C -4A
4.00mm max. Registered Normal Weak Driver 50 ODT Support 3.75ns* 5.0ns* 0.5ns* 0.6ns* 5.0ns* 0.6ns* 15ns 7.5ns
1 1
24
1
1 1
25 26 27 28
Minimum clock cycle time at CL = 3 Maximum data access time (tAC) from clock at CL = 3 Minimum row precharge time (tRP)
1
Minimum row active to row active delay 0 (tRRD)
Data Sheet E1052E30 (Ver.3.0)
5
EBE41RE4ACFA
Byte No. Function described 29 30 Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) -6E, -5C -4A 31 32 Module rank density Address and command setup time before clock (tIS) -6E -5C -4A 33 Address and command hold time after clock (tIH) -6E -5C -4A 34
Bit7 0 0 0 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
Bit5 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0
Bit4 1 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1
Bit3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0
Bit2 1 1 0 0 0 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0
Bit1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1
Bit0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 0
Hex value 3CH 2DH 28H 02H 20H 25H 35H 27H 37H 47H 10H 15H 17H 22H 27H 3CH 1EH 28H 1EH 00H 06H 3CH 37H 7FH 80H 18H 1EH 23H 22H 28H 2DH 0FH 00H 12H
Comments 15ns 45ns 40ns 2GB 0.20ns* 0.25ns* 0.35ns* 0.27ns* 0.37ns* 0.47ns* 0.10ns* 0.15ns* 0.17ns* 0.22ns* 0.27ns* 15ns*
1 1
1 1
1
1 1
Data input setup time before clock (tDS) 0 -6E, -5C -4A 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 SPD Revision 0 Data input hold time after clock (tDH) -6E -5C -4A
1
1
35
1
1 1
36 37
Write recovery time (tWR) Internal write to read command delay (tWTR) -6E, -5C -4A Internal read to precharge command delay (tRTP) Memory analysis probe characteristics Extension of Byte 41 and 42 Active command period (tRC) -6E, -5C -4A Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -6E -5C -4A
7.5ns* 10ns*
1
1
38 39 40 41
7.5ns* TBD
1
60ns* 55ns*
1
1
42 43 44
127.5ns* 8ns*
1
1
0.24ns* 0.30ns* 0.35ns* 0.34ns* 0.40ns* 0.45ns* 15s
1
1 1
45
Data hold skew (tQHS) -6E -5C -4A
1
1 1
46 47 to 61 62
PLL relock time
Rev. 1.2
Data Sheet E1052E30 (Ver.3.0)
6
EBE41RE4ACFA
Byte No. Function described 63 Checksum for bytes 0 to 62 -6E -5C -4A 64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -6E -5C -4A 87 Module part number -6E -5C -4A 88 89 90 91 92 93 94 95 to 98 Module part number Module part number Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number
Bit7 0 0 1 0 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x
Bit6 0 1 1 1 1 0 x 1 1 1 0 0 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 0 x x
Bit5 1 1 1 1 1 0 x 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 x x
Bit4 0 1 0 1 1 0 x 0 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 x x
Bit3 1 0 1 1 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 x x
Bit2 1 0 0 1 1 0 x 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0 x x
Bit1 0 0 1 1 1 0 x 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 x x
Bit0 1 1 1 1 0 0 x 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 x x
Hex value 2DH 71H EBH 7FH FEH 00H xx 45H 42H 45H 34H 31H 52H 45H 34H 41H 43H 46H 41H 2DH 36H 35H 34H 45H 43H 41H 2DH 45H 20H 30H 20H xx xx
Comments
Continuation code Elpida Memory
(ASCII-8bit code) E B E 4 1 R E 4 A C F A -- 6 5 4 E C A -- E (Space) Initial (Space) Year code (BCD) Week code (BCD)
99 to 127 Manufacture specific data
Note: 1. These specifications are defined based on component specification, not module.
Data Sheet E1052E30 (Ver.3.0)
7
EBE41RE4ACFA
Block Diagram
VSS /RCS1 /RCS0
DQS0 /DQS0
RS RS
DQS9
/DQS9
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DM /CS
4
RS
DQS /DQS
DM /CS
DQS /DQS
DQ0 to DQ3
RS RS
DQ0 to DQ3
D0
DQ0 to DQ3
D18
4
RS
DQ4 to DQ7
RS RS
DQ0 to DQ3
D9
DQ0 to DQ3
D27
DQS1 /DQS1
DQS10 /DQS10
DM /CS DQS /DQS DM /CS DQS /DQS
DQ8 to DQ11
4
RS
DM
/CS DQS /DQS
DM
/CS DQS /DQS
DQ0 to DQ3
D1
DQ0 to DQ3
D19
DQ12 to DQ15
4
RS
DQ0 to DQ3
D10
DQ0 to DQ3
D28
DQS2
/DQS2
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS11 /DQS11
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQ16 to DQ19
4
RS
DQ0 to DQ3
D2
DQ0 to DQ3
D20
DQ20 to DQ23
4
RS
DQ0 to DQ3
D11
DQ0 to DQ3
D29
DQS3
/DQS3
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS12 /DQS12
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQ24 to DQ27
4
RS
DQ0 to DQ3
D3
DQ0 to DQ3
4
D21
DQ28 to DQ31
RS RS
RS
DQ0 to DQ3
D12
DQ0 to DQ3
D30
DQS4
/DQS4
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS13 /DQS13
DM
/CS DQS /DQS
DM
/CS DQS /DQS
DQ32 to DQ35
4
RS
DQ0 to DQ3
D4
DQ0 to DQ3
D22
DQ36 to DQ39
4
RS
DQ0 to DQ3
D13
DQ0 to DQ3
D31
DQS5
/DQS5
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS14 /DQS14
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQ40 to DQ43
4
RS
DQ0 to DQ3
D5
DQ0 to DQ3
D23
DQ44 to DQ47
4
RS
DQ0 to DQ3
D14
DQ0 to DQ3
D32
RS
DQS6 /DQS6
RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS15 /DQS15
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQ48 to DQ51
4
RS
DQ0 to DQ3
D6
DQ0 to DQ3
D24
DQ52 to DQ55
4
RS
DQ0 to DQ3
D15
DQ0 to DQ3
D33
DQS7
/DQS7
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS16 /DQS16
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQ56 to DQ59
4
RS
DQ0 to DQ3
D7
DQ0 to DQ3
D25
DQ60 to DQ63
4
RS
DQ0 to DQ3
D16
DQ0 to DQ3
D34
DQS8
/DQS8
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
DQS17 /DQS17
RS RS
DM /CS DQS /DQS DM /CS DQS /DQS
CB0 to CB3
4
RS
DQ0 to DQ3
D8
DQ0 to DQ3
D26
CB4 to CB7
4
RS
DQ0 to DQ3
D17
DQ0 to DQ3
D35
/CS0*2 /CS1*2 BA0 to BA2 A0 to A13 /RAS /CAS CKE0 CKE1 /WE /ODT0 /ODT1
RS
RS
/RCS0 -> /CS: SDRAMs D0 to D17 /RCS1 -> /CS: SDRAMs D18 to D35 R E G I S T E R RBA0 to RBA2 -> BA0 to BA2: SDRAMs D0 to D35 RA0 to RA13 -> A0 to A13: SDRAMs D0 to D35 /RRAS -> /RAS: SDRAMs D0 to D35 /RCAS -> /CAS: SDRAMs D0 to D35 RCKE0 -> CKE: SDRAMs D0 to D17 RCKE1 -> CKE: SDRAMs D18 to D35 /RWE -> /WE: SDRAMs D0 to D35 RODT0 -> ODT: SDRAMs D0 to D17
/RST
Serial PD
SCL SCL SDA
RS
RS
RS
RS
RS
RS
RS
RS RS
SDA
U0
WP A0 A1 A2
D0 to D35: 1G bits DDR2 SDRAM U0: 2k bits EEPROM RS: 22 PLL: CUA877 Register: SSTUB32868
SA0 SA1 SA2
VDDSPD
VDD
Serial PD D0 to D35 D0 to D35 D0 to D35
RODT1 -> ODT: SDRAMs D18 to D35
VREF VSS
/RESET*3 PCK7*3
/PCK7*3
CK0 /CK0 /RESET P L L OE
Notes: 1. DQ wiring may be changed within a nibble. 2. /CS0 connects to /DCS on register1 and /CSR on register2 /CS1 connects to /CSR on register1 and /DCS on register2 3. /RESET, PCK7 and /PCK7 connect to all registers. CKE and /ODT connect to a register. Other signals connect to one of two registers.
PCK0 to PCK6, PCK8, PCK9 -> CK: SDRAMs D0 to D35 /PCK0 to /PCK6, /PCK8, /PCK9 -> /CK: SDRAMs D0 to D35
PCK7 -> CK: register /PCK7 -> /CK: register
Data Sheet E1052E30 (Ver.3.0)
8
EBE41RE4ACFA
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal) SDRAM PLL OUT1 SDRAM CK0 120 IN /CK0 SDRAM SDRAM
120
Register 1
C
120
120 C
OUT'N' Feedback in Feedback out
Register 2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Data Sheet E1052E30 (Ver.3.0)
9
EBE41RE4ACFA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to +2.3 -0.5 to +2.3 50 18 0 to +95 -55 to +100 Unit V V mA W C C 1, 2 1 1 Notes 1
Notes: 1. DDR2 SDRAM component specification. 2. Supporting 0C to +85C and being able to extend to +95C with doubling auto-refresh commands in frequency to a 32ms period (tREFI = 3.9s) and higher temperature self-refresh entry via the control of EMRS (2) bit A7 is required. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC Operating Conditions (TC = 0C to +85C) (DDR2 SDRAM Component Specification)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Termination voltage DC input logic high DC input low AC input logic high -6E -5C, -4A AC input low -6E -5C, -4A VREF VTT VIH (DC) VIL (DC) VIH (AC) VIH (AC) VIL (AC) VIL (AC) min. 1.7 0 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 VREF + 0.200 VREF + 0.250 typ. 1.8 0 -- max. 1.9 0 3.6 Unit V V V V V V V V V V V 1, 2 3 Notes 4
0.50 x VDDQ 0.51 x VDDQ VREF VREF + 0.04 VDDQ + 0.3 VREF - 0.125 VREF - 0.200 VREF - 0.250
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD.
Data Sheet E1052E30 (Ver.3.0)
10
EBE41RE4ACFA
AC Overshoot/Undershoot Specification (DDR2 SDRAM Component Specification)
Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD DDR2-667 DDR2-533 DDR2-400 Maximum undershoot area below VSS DDR2-667 DDR2-533 DDR2-400 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD DDR2-667 DDR2-533 DDR2-400 Maximum undershoot area below VSS DDR2-667 DDR2-533 DDR2-400 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDDQ DDR2-667 DDR2-533 DDR2-400 Maximum undershoot area below VSSQ DDR2-667 DDR2-533 DDR2-400 DQ, DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS, RDQS, /RDQS, DM, UDM, LDM CK, /CK Pins Command, Address, CKE, ODT Specification 0.5 0.5 0.8 1.0 1.33 0.8 1.0 1.33 0.5 0.5 0.23 0.28 0.38 0.23 0.28 0.38 0.5 0.5 0.23 0.28 0.38 0.23 0.28 0.38 Unit V V V-ns V-ns V-ns V-ns V-ns V-ns V V V-ns V-ns V-ns V-ns V-ns V-ns V V V-ns V-ns V-ns V-ns V-ns V-ns
Maximum amplitude Overshoot area
Volts (V)
VDD, VDDQ VSS, VSSQ
Undershoot area
Time (ns)
Overshoot/Undershoot Definition
Data Sheet E1052E30 (Ver.3.0)
11
EBE41RE4ACFA
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.8V 0.1V, VSS = 0V)
Parameter Symbol Grade -6E -5C -4A max. 3457 3052 2737 Unit Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0
Operating current (ACT-PRE)
IDD0
mA
Operating current (ACT-READ-PRE)
IDD1
-6E -5C -4A
3842 3405 3059
mA
Precharge power-down standby current
IDD2P
-6E -5C -4A
895 850 805
mA
Precharge quiet standby current
IDD2Q
-6E -5C -4A
1615 1390 1345
mA
Idle standby current
IDD2N
-6E -5C -4A
1795 1570 1345 1795 1570 1525 1255 1210 1165
mA
Active power-down standby current
-6E IDD3P-F -5C -4A -6E IDD3P-S -5C -4A
mA
mA
Slow PDN Exit MRS(12) = 1
Active standby current
IDD3N
-6E -5C -4A
3457 2872 2467
mA
all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating current (Burst read operating)
IDD4R
-6E -5C -4A
4652 3945 3329
mA
Operating current (Burst write operating)
IDD4W
-6E -5C -4A
4652 3945 3329
mA
Data Sheet E1052E30 (Ver.3.0)
12
EBE41RE4ACFA
Parameter
Symbol
Grade -6E -5C -4A
max. 7033 6538 6133
Unit
Test condition tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK(IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tFAW = tFAW (IDD), tRCD = 1 x tCK (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Auto-refresh current
IDD5
mA
Self-refresh current
IDD6
371
mA
Operating current (Bank interleaving)
IDD7
-6E -5C -4A
7551 6840 6221
mA
Notes: 1. 2. 3. 4.
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS and /RDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667 Parameter CL (IDD) tRCD (IDD) tRC (IDD) tRRD (IDD) tFAW (IDD) tCK (IDD) tRAS (min.)(IDD) tRAS (max.)(IDD) tRP (IDD) tRFC (IDD) 5-5-5 5 15 60 7.5 37.5 3 45 70000 15 127.5 DDR2-533 4-4-4 4 15 60 7.5 37.5 3.75 45 70000 15 127.5 DDR2-400 3-3-3 3 15 55 7.5 37.5 5 40 70000 15 127.5 Unit tCK ns ns ns ns ns ns ns ns ns
Data Sheet E1052E30 (Ver.3.0)
13
EBE41RE4ACFA
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
Notes: 1. 2. 3. 4. 5.
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TC = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter AC differential input voltage AC differential cross point voltage AC differential cross point voltage Symbol VID (AC) VIX (AC) VOX (AC) min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125 max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125 Unit V V V Notes 1, 2 2 3
Notes: 1. VID (AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, RDQS) and VCP is the complementary input signal (such as /CK, /DQS, /RDQS). The minimum value is equal to VIH (AC) - VIL (AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
VDDQ VTR
VID
VCP VSSQ
Crossing point
VIX or VOX
Differential Signal Levels*1, 2
Data Sheet E1052E30 (Ver.3.0)
14
EBE41RE4ACFA
ODT DC Electrical Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Rtt effective impedance value for EMRS (A6, A2) = 1, 1; 50 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) Rtt3(eff) VM min. 60 120 40 -6 typ. 75 150 50 max. 90 180 60 +6 Unit % Note 1 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt (eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18.
Rtt (eff ) =
VIH ( AC ) - VIL( AC ) I (VIH ( AC )) - I (VIL( AC ))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
2 x VM - 1 x 100 VM = VDDQ
OCD Default Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Output impedance Pull-up and pull-down mismatch Output slew rate min. 12.6 0 1.5 typ. 18 max. 23.4 4 5 Unit V/ns Notes 1, 5 1, 2 3, 4
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization. 5. DRAM I/O specifications for timing, voltage, and slew rate are no longer applicable if OCD is changed from default settings. Pin Capacitance (TA = 25C, VDD = 1.8V 0.1V)
Parameter Input capacitance Input capacitance Input/output pin capacitance -6E -5C, -4A Symbol CI1 CI2 CI/O Pins Address, /RAS, /CAS, /WE, /CS, CKE, ODT CK, /CK DQ, DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS, RDQS, /RDQS, DM, UDM, LDM, CB min. 2.0 2.0 2.5 2.5 max. 3.5 3.0 3.5 4.0 Unit pF pF pF pF Notes 1 2 3 3
Notes: 1. Register component specification. 2. PLL component specification. 3. DDR2 SDRAM component specification.
Data Sheet E1052E30 (Ver.3.0)
15
EBE41RE4ACFA
AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.8V 0.1V, VSS, VSSQ = 0V) [DDR2-667] (DDR2 SDRAM Component Specification) * New units tCK(avg) and nCK, are introduced in DDR2-800 and DDR2-667 tCK(avg): actual tCK(avg) of the input clock under operation. nCK: one clock cycle of the input clock, counting the actual clock edges.
-6E Speed bin Parameter Active to read or write command delay Precharge command period Active to active/auto-refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Clock cycle time (CL = 6) (CL = 5) (CL = 4) (CL = 3) DQ and DM input hold time DQ and DM input setup time Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK DQS, /DQS low-impedance time from CK,/CK DQ low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Symbol tRCD tRP tRC tAC tDQSCK tCH (avg) tCL(avg) tHP tCK (avg) tCK (avg) tCK (avg) tCK (avg) tDH (base) tDS (base) tIPW tDIPW tHZ tLZ (DQS) tLZ (DQ) tDQSQ tQHS tQH DDR2-667 (5-5-5) min. 15 15 60 -450 -400 0.48 0.48 Min. (tCL(abs), tCH(abs)) 3000 3000 3750 5000 175 100 0.6 0.35 tAC min. 2 x tAC min tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 275 200 0.9 0.4 max. +450 +400 0.52 0.52 8000 8000 8000 8000 tAC max. tAC max. tAC max. 240 340 +0.25 0.6 1.1 0.6 Unit ns ns ns ps ps tCK (avg) tCK (avg) ps ps ps ps ps ps ps tCK (avg) tCK (avg) ps ps ps ps ps ps tCK (avg) tCK (avg) tCK (avg) tCK (avg) tCK (avg) nCK tCK (avg) tCK (avg) ps ps tCK (avg) tCK (avg) 5 4 11 12 7 8 10 10 10 10 10 13 13 6, 13 13 13 13 13 5 4 Notes
DQS latching rising transitions to associated clock tDQSS edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH (base) tIS (base) tRPRE tRPST
Data Sheet E1052E30 (Ver.3.0)
16
EBE41RE4ACFA
-6E Speed bin Parameter Active to precharge command Active to auto-precharge delay Active bank A to active bank B command period Four active window period /CAS to /CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self-refresh to a non-read command Exit self-refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay MRS command to ODT update delay Symbol tRAS tRAP tRRD tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tOIT
tMOD
DDR2-667 (5-5-5) min. 45 tRCD min. 7.5 37.5 2 15 WR + RU (tRP/ tCK (avg)) 7.5 7.5 tRFC + 10 200 2 2 7 - AL 3 0 0 127.5 tIS + tCK(avg) + tIH max. 70000 12 12 7.8 3.9 Unit ns ns ns ns nCK ns nCK ns ns ns nCK nCK nCK nCK nCK ns ns ns s s ns 3 2, 3 1, 9 Notes
Auto-refresh to active/auto-refresh command time tRFC Average periodic refresh interval (0C TC +85C) (+85C < TC +95C) Minimum time clocks remains ON after CKE asynchronously drops low tREFI tREFI tDELAY
Data Sheet E1052E30 (Ver.3.0)
17
EBE41RE4ACFA
AC Characteristics [DDR2-533, 400]
-5C Speed bin Parameter Active to read or write command delay Precharge command period Active to active/auto-refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Clock cycle time (CL = 6) (CL = 5) (CL = 4) (CL = 3) DQ and DM input hold time (differential strobe) DQ and DM input hold time (single-ended strobe) DQ and DM input setup time (differential strobe) DQ and DM input setup time (single-ended strobe) Control and Address input pulse width for each input Symbol tRCD tRP tRC tAC tDQSCK tCH tCL tHP tCK tCK tCK tCK DDR2-533 (4-4-4) min. 15 15 60 -500 -450 0.45 0.45 Min. (tCL, tCH) 3750 3750 3750 5000 max. +500 +450 0.55 0.55 8000 8000 8000 8000 tAC max. tAC max. 300 400 -4A DDR2-400 (3-3-3) min. 15 15 55 -600 -500 0.45 0.45 Min. (tCL, tCH) 5000 5000 5000 5000 275 +25 150 +25 0.6 0.35 tAC min. max. +600 +500 0.55 0.55 8000 8000 8000 8000 tAC max. tAC max. 350 450 Unit ns ns ns ps ps tCK tCK ps ps ps ps ps ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns 5 4 4 5 Notes
tDH (base) 225 tDH1 (base) -25
tDS (base) 100 tDS1 (base) tIPW -25 0.6 0.35 tAC min.
DQ and DM input pulse width for each input tDIPW Data-out high-impedance time from CK,/CK tHZ Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS tLZ tDQSQ tQHS tQH
tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 +0.25 0.6 1.1 0.6 70000
tHP - tQHS -0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 475 350 0.9 0.4 40 +0.25 0.6 1.1 0.6 70000
DQS latching rising transitions to associated tDQSS clock edges DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Active to precharge command tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE
tIH (base) 375 tIS (base) 250 tRPRE tRPST tRAS 0.9 0.4 45
Data Sheet E1052E30 (Ver.3.0)
18
EBE41RE4ACFA
-5C Speed bin Parameter Active to precharge command Active to auto-precharge delay Active bank A to active bank B command period Four active window period /CAS to /CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self-refresh to a non-read command Exit self-refresh to a read command Symbol tRAS tRAP tRRD tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD DDR2-533 (4-4-4) min. 45 tRCD min. 7.5 37.5 2 15 max. 70000 -4A DDR2-400 (3-3-3) min. 40 tRCD min. 7.5 37.5 2 15 max. 70000 Unit ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns ns s s ns 3 2, 3 1, 9 Notes
WR + RU(tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 6 - AL 3 0 0 127.5 tIS + tCK + tIH 12 12 7.8 3.9
WR + RU(tRP/tCK) 10 7.5 tRFC + 10 200 2 2 6 - AL 3 0 0 127.5 tIS + tCK + tIH 12 12 7.8 3.9
Exit precharge power-down to any non-read tXP command Exit active power-down to read command Exit active power-down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay MRS command to ODT update delay tXARD tXARDS tCKE tOIT
tMOD
Auto-refresh to active/auto-refresh command tRFC time Average periodic refresh interval tREFI (0C TC +85C) (+85C < TC +95C) tREFI Minimum time clocks remains ON after CKE tDELAY asynchronously drops low
Notes: 1. 2. 3. 4.
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
CK /CK
DQS /DQS
tDS
tDH
tDS
tDH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
tIS
tIH
tIS
tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E1052E30 (Ver.3.0)
19
EBE41RE4ACFA
6. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = min ( tCH(abs), tCL(abs) ), where, tCH(abs) is the minimum of the actual instantaneous clock high time; tCL(abs) is the minimum of the actual instantaneous clock low time; 7. tQHS accounts for: a. The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and b. The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers. 8. tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: a. If the system provides tHP of 1315ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975ps (min.) b. If the system provides tHP of 1420ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080ps (min.) 9. RU stands for round up. WR refers to the tWR parameter stored in the MRS. 10. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = -272ps and tERR(6-10per) max. = +293ps, then tDQSCK min.(derated) = tDQSCK min. - tERR(6-10per) max. = -400ps - 293ps = -693ps and tDQSCK max.(derated) = tDQSCK max. - tERR(6-10per) min. = 400ps + 272ps = +672ps. Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ) min.(derated) = -900ps - 293ps = -1193ps and tLZ(DQ) max.(derated)= 450ps + 272ps = +722ps. 11. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per) min. = -72ps and tJIT(per) max. = +93ps, then tRPRE min.(derated) = tRPRE min. + tJIT(per) min. = 0.9 x tCK(avg) - 72ps = +2178ps and tRPRE max.(derated) = tRPRE max. + tJIT(per) max. = 1.1 x tCK(avg) + 93ps = +2843ps. 12. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty) min. = -72ps and tJIT(duty) max. = +93ps, then tRPST min.(derated) = tRPST min. + tJIT(duty) min. = 0.4 x tCK(avg) - 72ps = +928ps and tRPST max.(derated) = tRPST max. + tJIT(duty) max. = 0.6 x tCK(avg) + 93ps = +1592ps. 13. Refer to the Clock Jitter table.
Data Sheet E1052E30 (Ver.3.0)
20
EBE41RE4ACFA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter ODT turn-on delay ODT turn-on -6E -5C, -4A ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min. 2 tAC(min) tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max. 2 tAC(max) + 700 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps ps tCK ps ps tCK tCK 5, 6 2, 4, 5, 6 1, 3 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. 3. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) 4. When the device is operated with input clock jitter, this parameter needs to be derated by {-tJIT(duty) max. - tERR(6-10per) max. } and { -tJIT(duty) min. - tERR(6-10per) min. } of the actual input clock.(output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per) min. = -272ps, tERR(6-10per) max. = +293ps, tJIT(duty) min. = -106ps and tJIT(duty) max. = +94ps, then tAOF min.(derated) = tAOF min. + { -tJIT(duty) max. - tERR(6-10per) max. } = -450ps + { -94ps - 293ps} = -837ps and tAOF max.(derated) = tAOF max. + { -tJIT(duty) min. - tERR(6-10per) min. } = 1050ps + { 106ps + 272ps} = +1428ps. 5. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock high pulse width of 0.5 relative to tCK. tAOF min. and tAOF max. should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45, the tAOF min. should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of 0.55, the tAOF max. should be derated by adding 0.05 x tCK to it. Therefore, we have; tAOF min.(derated) = tAC min. - [0.5 - Min.(0.5, tCH min.)] x tCK tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH max.) - 0.5] x tCK or tAOF min.(derated) = Min.(tAC min., tAC min. - [0.5 - tCH min.] x tCK) tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH max. - 0.5] x tCK) where tCH min. and tCH max. are the minimum and maximum of tCH actually measured at the DRAM input balls. 6. For tAOFD of DDR2-667, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock high pulse width of 0.5 relative to tCK(avg). tAOF min. and tAOF max. should each be derated by the same amount as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH(avg) of 0.48, the tAOF min. should be derated by subtracting 0.02 x tCK(avg) from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF max. should be derated by adding 0.02 x tCK(avg) to it. Therefore, we have; tAOF min.(derated) = tAC min. - [0.5 - Min.(0.5, tCH(avg) min.)] x tCK(avg) tAOF max.(derated) = tAC max. + 0.6 + [Max.(0.5, tCH(avg) max.) - 0.5] x tCK(avg) or tAOF min.(derated) = Min.(tAC min., tAC min. - [0.5 - tCH(avg) min.] x tCK(avg)) tAOF max.(derated) = 0.6 + Max.(tAC max., tAC max. + [tCH(avg) max. - 0.5] x tCK(avg)) where tCH(avg) min. and tCH(avg) max. are the minimum and maximum of tCH(avg) actually measured at the DRAM input balls.
Data Sheet E1052E30 (Ver.3.0)
21
EBE41RE4ACFA
AC Input Test Conditions (DDR2 SDRAM Component Specification)
Parameter Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL (AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min. for rising edges and the range from VREF to VIL(AC) max. for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH (AC)(min.) VIH (DC)(min.)
VSWING(max.)
VREF VIL (DC)(max.) VIL (AC)(max.)
TF Falling slew = VREF
TR
Rising slew =
VSS
VIH (AC) min. - VREF TR
- VIL (AC)(max.)
TF
AC Input Test Signal Wave forms
Measurement point
DQ RT =25
VTT
Output Load
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
Clock Jitter [DDR2-667]
-6E Frequency (Mbps) Parameter Average clock period Clock period jitter Clock period jitter during DLL locking period Cycle to cycle period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across n=6,7,8,9,10 cycles Cumulative error across n=11, 12,...49,50 cycles Average high pulse width Average low pulse width Duty cycle jitter Symbol tCK (avg) tJIT (per) tJIT (per, lck) tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6-10per) tERR (11-50per) tCH (avg) tCL (avg) tJIT (duty) 667 min. 3000 -125 -100 -175 -225 -250 -250 -350 -450 0.48 0.48 -125 max. 8000 125 100 250 200 175 225 250 250 350 450 0.52 0.52 125 Unit ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) ps Notes 1 5 5 6 6 7 7 7 7 7 7 2 3 4
Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window.
N tCK (avg ) = tCKj N j =1
N = 200 2. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses.
N tCH (avg ) = tCHj (N x tCK (avg )) j =1
N = 200 3. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.
N tCL(avg ) = tCLj (N x tCK (avg )) j =1
N = 200 4. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where: tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200} tJIT (CL) = {tCLj - tCL (avg) where j = 1 to 200} 5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCKj - tCK (avg) where j = 1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production test.
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
6. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT (cc) = Max. of |tCKj+1 - tCKj| tJIT (cc) is defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production test. 7. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production test.
n tERR(nper ) = tCKj - n x tCK(avg )) j =1
2 n 50 for tERR (nper) 8. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.)
Parameter Absolute clock period Absolute clock high pulse width Absolute clock low pulse width Symbol tCK (abs) tCH (abs) tCL (abs) min. tCK (avg) min. + tJIT (per) min. tCH (avg) min. x tCK (avg) min. + tJIT (duty) min. tCL (avg) min. x tCK (avg) min. + tJIT (duty) min. max. Unit tCK (avg) max. + tJIT (per) max. ps tCH (avg) max. x tCK (avg) max. ps + tJIT (duty) max. tCL (avg) max. x tCK (avg) max. ps + tJIT (duty) max.
Example: For DDR2-667, tCH(abs) min. = ( 0.48 x 3000 ps ) - 125ps = 1315ps
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
Pin Functions
CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9 and A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0, BA1, BA2 (input pin) BA0, BA1 and BA2 are bank select signals (BA). The memory array is divided into 8 banks: bank 0 to bank 7. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H
Remark: H: VIH. L: VIL.
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH. DQ, CB (input and output pins) Data are input to and output from these pins. DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input). VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. /RESET(input pin) LVCMOS reset input. When /RESET is Low, all registers are reset. Par_IN (Parity input pin) Parity bit for the address and control bus. /Err_Out (Error output pin) Parity error found on the address and control bus.
Detailed Operation Part and Timing Waveforms
Refer to the EDE1104ACSE, EDE1108ACSE, EDE1116ACSE datasheet (E0975E). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = component CL + 1 for registered type.
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
Physical Outline
Unit: mm
4.00 max (DATUM -A-)
0.5 min
Component area (Front)
1 120
B 63.00 133.35 55.00
A 1.27 0.10
240
10.00
121
17.80
4.00 min
Component area (Back)
4.00
FULL R
3.00
Detail A
2.50 0.20
Detail B 1.00 4.00
0.20 0.15
(DATUM -A-)
2.50 FULL R
5.00
3.80
0.80 0.05
1.50 0.10
ECA-TS2-0093-01
Data Sheet E1052E30 (Ver.3.0)
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30.00
EBE41RE4ACFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E1052E30 (Ver.3.0)
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EBE41RE4ACFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Data Sheet E1052E30 (Ver.3.0)
29

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